Electronic digital computer



March 14-, 1961 F. G. STEELE 2,974,357

ELECTRONIC DIGITAL COMPUTER Filed Oct. 25, 1956 4 Sheets-Sheet 1 fl'ec/m: 1

07 Mar/r /'x F/yd 6. lee e March 14, 1961 F. G. STEELE 2,974,867

ELECTRONIC DIGITAL COMPUTER Filed Oct. 25, 1956 4 Sheets-Sheet 2 WEE? E E E E E E w NLEEN E March 14, 1961 STEELE 2,974,867

ELECTRONIC DIGITAL COMPUTER Filed Oct. 25, 1956 4 Sheets-Sheet 3 March 14, 1961 F S E LE 2,974,867

ELECTRONIC DIGITAL COMPUTER Filed 001.. 25, 1956 4 Sheets-Sheet 4 United States Patent Ofice 2,974,867 Patented Mar. 14, 1961 ELECTRONIC DIGITAL COMPUTER Floyd G. Steele, La Jolla, Calif., assignor to Digital Control Systems, Inc., La Jolla, Calif.

Filed Oct. 25, 1956, Ser. No. 618,232 28 Claims. (Cl. 235-167) The present invention relates to an electronic digital computer and more particularly to a general purpose electronic digital serial computer wherein both the number of addressing operations required and the equipment required for the accomplishment of such addressing operations has been greatly reduced.

In recent years a number of general purpose computers have been constructed, which although utilizing a fairly slow serial type of storage of signals, namely, magnetic drum storage, have nevertheless achieved unusually high computational rates, these high computational rates being largely due to the fact that these machines operate in a basic single address mode of operation which encourages minimal time programming and which eliminates much of the transferring, searching and selecting associated with the older two, three and four address modes of operation.

In one of the most advanced of these prior art computers, the information stored in the internal memory of the computer is organized in the following manner. The largest unit of information stored in the computer is called a block. A block comprises a plurality of serially arranged words, there being two types of words, instruction words and operand words. As instruction word contains a first group of signals designating an instruction to be performed and a second group of signals designating the address or position in the memory from which is to be read an operand number required in performing the instruction. An operand word contains merely a group of signals designating an operand number.

The memory of this prior art computer is organized into three one word arithmetic or operating registers (which are mechanized as short recirculating memory channels established over segments of the drum surface), an intermediate memory which contains four blocks contained in four separate intermediate length channels, and a main memory which contains a very large number of blocks each stored in a separate channel of the drum and read by a separate transducer.

Computation is ordinarily performed upon the words of one of the four blocks stored in the intermediate memory, the other three blocks being held in a stand-by condition so that they are ready for use when required. In a block being computed upon, instruction words are stored in a definite order and in predetermined positions or addresses, each instruction word being spaced from the preceding instruction word by a distance corresponding to A; revolution of the drum. The spaces between the instruction words contain operand words. The normal operation of the computer is that it reads and accepts the instruction words in order. In response to the instruction and address in each instruction word, the computer waits until the operand number designated by the address appears at the read transducer. The designated operand number is then copied into one of the arithmetic registers and combined with numbers in the other arithmetic registers in accordance with the mathematical operation designated by the instruction. Alternatively, in response to an instruction and associated address, a number may be copied from one of the arithmetic registers into the intermediate length channel at the position designated by the address. The normal serial order in which instruction words are read may be disrupted through use of a jump instruction and associated address, the jump instruction causing the computer to not accept the normal succeeding instruction word but rather to accept its next instruction word from the position designated by the address.

Certain instructions called no address instructions specify operations to be performed only between arithmetic registers and hterefore do not require any new operands. In responding to such a no address instruction the computer ignores the following address and merely performs the required inter-register operation. The unused address may be replaced if desired by an additional no address instruction.

It should be understood that word addressing of the type described above is restricted to the block being computed upon in the intermediate channel. Special block jump instructions are provided which can cause the computer to begin computing upon a dilferent one of the four blocks of the intermediate memory. When new information must be summoned up from the main memory, a block copy instruction and associated address are utilized, the address designating not a word position but rather the channel in the main memory in which the described block is stored. In response to a block copy instruction and associated address the computer parallel selects by means of a set of relays the transducer which is reading the channel of the desired block in the main memory and that block is then copied into one of the four blocks of the intermediate memory. Block copy instructions are also available for copying blocks back from the inter mediate memory channels into designated channels of the main memory.

Word addressing in this prior art computer in connection with normal signal address instructions is mechanized in the following manner. A word address is transferred from the instruction word in which it appears to a plurality of flip-flops comprising an address register. The number in the address register is then continually compared with the count in a word counter which is counting words passing beneath the read transducer of the block being computed upon. When the count in the Word counter agrees with the number in the address register, it is known that the desired word is being read and it is copied into one of the arithmetic registers.

Block addressing, in connection with a block copy instruction is mechanized in a somewhat different manner. A block address is transferred just like a word address to the address register. The output signals of the address register flip-flops are then utilized in parallel to control the selection, by means of a set of relays, of the transducer on the designated channel of the main memory. Since there are a very large number of channels in the main memory, a rather large selection matrix are a large number of relays and associated transducers (as well as the flip-flops of the address register) are required to accomplish this parallel selection of a desired block from the main memory. The equipment required in the described prior art computer for accomplishing this parallel selection constitutes a relatively large proportion of the total equipment in the computer.

It is of course obvious that it is desirable from an economic viewpoint to decrease the amount of equipment in a computer. especially if this can be done without any impairment of performance especially as respects speed of operation. The general purpose computer of the present invention has less than half as much equipment as the described prior art computer. In the general purpose computer of the present invention, the flip-flops of the word counter; and of the address register, and the large amount of equipment (selection matrix, multiplicity of relays and multiplicity of transducers) required for parallel selections of blocks from the multiple channels of the main memory has been entirely eliminated. Nevertheless the performance parameters of the general purpuse computer of the present invention in general match and in some areas exceed those of the described prior art computer, the computer of the present invention having approximately the same effective operating speed as the descirbed prior art computer and having similar types and varieties of instructions as well as certain special instructions which greatly increase its flexibility.

In the computer of the present invention very nearly all of the large amount of equipment normally required for selection of blocks from the main memory has been eliminated by serializing the main memory. That is, in the computer of the present invention, the plurality of blocks of the main memory are not contained in separate channels on the drum, each read by a separate parallel selected transducer but are instead arranged in order in a long memory channel or loop, the blocks being read in serial order from the long channel by an associated read transducer.

Parallel selection of the proper read transducer for a desired block is therefore not required in the computer of the present invention, a desired block being obtained instead, by calling for it at the time that it is being read by the read transducer of the long channel. The manner in which the long channel is established is unique. To assure absolute synchronization between the long channel and the other channels of the computer, the long channel is established on the surface of the drum itself, this being accomplished by gearing two transducers to the drum so that they are moved axially upwards and downwards adjacent the drum, each trans ducer traversing a helical channel on the drum surface, a counterclockwise helical channel being traversed by one transducer as the transducers move upward and an oppositely wound clockwise helical channel being traversed by the other transducer as the transducers move downwards. These two helical channels together hold all of the blocks of the main memory, so that all of the blocks of the main memory are traversed in order during one cycle of movement of the transducers. The coupling between the transducers and the drum is such that one traversal (one cycle of operation) of the long channel corresponds to an integral number of drum revolutions thus assuring that the helical channels and the blocks stored therein have fixed and known positions on the drum periphery. The two transducers are alternately connected by a switch to a common read-write circuit, each transducer being connected as it traverses its own helical channel.

It might be thought that serializing the main memory would have the eifect of considerably reducing operating speed, since it is necessary to wait for a desired main memory block until it is read in its normal serial order rather than directly and immediately selecting the desired block. Actually there is no decrease in effective operating speed in the general purpose computer of the present invention. It must be understood in this connection that in ordinary computation, new blocks are required relatively infrequently. Ordinarily, lengthy computations, extensive iterations, are performed on the words of a block being computed upon, a new block not being required until these lengthy computations have been completed.

It is therefore clear that even a moderate increase in speed of computation upon words of a block will compensate for considerable increase in the time required for obtaining new blocks. Such an increase in speed of computation upon words of a block being computed upon has actually been obtained in the computer of the present invention by designating it to normally operate in a basic no-address mode of operation which occasionally reverts to a modified form of single address. In this form of operation called half-address operation, all words are instruction words and are normally read in order from an L block held in an intermediate channel. Each word contains an instruction and immediately thereafter a number portion designating an operand (and occasionally designating an address or addresses). When such a word is read, the instruction contained in the word is performed upon the immediately succeeding operand in the same word. Thus, ordinarily, addressing operations are not required and all of the time required in a single address operation for reading the address and seeking the addressed operand word is saved.

A few special instructions notably the jump instruction and the so-called put" and take" instruction require addresses and in a word containing such an instruction the immediately succeeding number portion (now and address portion) designates the address or addresses. In contrast to the described prior art computer, it is seen that in the computer of the present invention no address operation is not restricted to a necessarily brief series of instructions acting upon the few operands in the arithmetic registers but rather can proceed continuously for a great many instructions because of the fact that a large number of new operands can be introduced, as computation proceeds, thereby saving considerable time. It is quite feasible for example, in the general purpose computer of the present invention to perform 32 operational instructions during one cycle of operations upon a 33 word block, a computational rate that is unexcelled.

Moreover, since no address functioning is the normal mode of operation of the computer of the present invention, it is clear that an address register is not normally required. In fact there is no address register at all in the present computer. None is required in the normal no address operation and in response to an occasional word holding a special instruction and address portion, one of the arithmetic registers is borrowed to temporarily hold the address portion while the desired address (or addresses) is being found.

It should be said in this connection that the way in which addresses are designated by the signals of an address portion of a word is unique, and that virtually no equipment is required for locating desired words in accordance with such an address portion. The signals of an address portion of a word in a block correspond respectively to the words of the block. Thus a desired word may be addressed by the single signal positioned in a corresponding signal location (cell) of an address portion of a word. Extending this further it is clear that a plurality of desired words may be addressed by a corresponding plurality of signals positioned in the corresponding cells of an address portion. This latter fea ture makes possible certain very unusual and useful instructions. For example in response to a so-called Put in L instruction in a word of the L block, a number in an arithmetic register X is copied into any number of words in the L block, as arbitrarily designated by signals positioned in corresponding cells of the address portion of the word containing the Put instruction. Instructions of this type have been found to be exceedingly useful and are not available in any prior art computer.

In addition to the use of the described normal no address mode of operation, other features have been incorporated into the computer of the present invention to increase its effective computational speed and reduce equipment requirements. To eliminate any waste of time in reading a new block from the main memory, a system is used in which new blocks are read out of the main memory in advance of need, each block being stored in a standby condition in the intermediate channel as a B block which is interplexed digit by digit with the L block being computed upon. When computation upon the L block is completed, the L and B blocks are interchanged so that the standby B block enters computation without any delay as a new L block.

It should be understood that the reading of a new standby B block in advance of need from the main memory is automatically accomplished by the computer without any cessation of the computations being performed upon the words of the L block and without requiring the use of any special block copy instructions in the L block. Moreover almost no equipment is required to identify and select such standby blocks from the main memory. Blocks in the main memory are arranged in groups called precincts. The words in a block correspond respectively to the blocks in a precinct. Each block in the main memory carries the address of its successor block by having a single binary signal t positioned in the corresponding word of the block. Thus for example if block 3 is to be automatically followed by block 12, then block 3 will have signal 1,, positioned in word 12. When block 3 is being computed upon as an L block, the computer will automatically respond to signal t in Word 12 (W12) and will cause Block 12 (B112) to be read out of the main memory as a B block as soon as it appears beneath the main memory transducer. The unique manner in which is accomplished the identification and reading of blocks from the main memory in response to the t signals will be described in detail hcreinbelow.

It should be noted that in the specific embodiment of the invention described hereinbelow each t signal utilized to control the reading of a successor block is retained for a while thereafter and later controls the return or writing of the successor block into its original position in the main memory. The normal order of succession of blocks may be changed through use of a Branch instruction which allows a block to be followed by an alternate successor block rather than its normal successor block.

It is therefore an object of the present invention to provide an electronic digital computer requiring virtually no equipment for the performance of addressing operations.

It is another object of the invention to provide a general purpose computer functioning in a basic no-address mode of operation.

It is still another object of the invention to provide a general purpose computer wherein each word comprises an instruction and a number portion normally designating an operand, the computer responding to each instruction by operating upon the operand in the same word in accordance with the instruction.

It is yet another object of the invention to provide an electronic digital computer wherein the signals of an address portion of a word correspond respectively to Words in a block, the computer being responsive to each signal in the address portion for operating upon the corresponding word.

It is a further object of the present invention to provide an electronic digital computer having a serialized main memory exactly and absolutely synchronized with its intermediate memory.

It is still another object of the present invention to provide a magnetic drum electronic digital computer having a serialized main memory comprising two helical channels established over the periphery of the drum by transducers coupled to the drum and moving in synchronism therewith.

It is a further object of the present invention to provide an electronic digital computer wherein, While a block is being computed upon, a successor block is automatically read from a serialized main memory into the intermediate memory to serve in a standby capacity.

It is yet another object of the present invention to provide an electronic digital computer wherein Words are grouped in blocks and blocks are grouped in precincts, the words in a block corresponding respectively to the blocks in a precinct, each block having a successor block and having a signal t positioned in the corresponding one of its words to designate the successor block.

It. is still another object of the present invention to provide a computer wherein a standby B block is interplexed digit by digit in the intermediate channel with an L block being computed upon, whereby the two blocks may be exchanged without delay when computation on the L block is completed.

The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages thereof, will be better understood from the following description considered in connection with the accompanying drawings in which one embodiment of the invention is illustrated by way of example. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only, and are not intended as a definition of the limits of the invention.

Fig. 1 is a partly block, partly circuit diagram of a preferred embodiment of the electronic digital computer of the present invention;

Fig. 2 is a plan view partly in section of the transducer moving mechanism which is utilized in the preferred embodiment of the computer of the present invention;

Fig. 3 is a word structure diagram which sets forth the manner in which signals are arranged in the memory channels of the preferred embodiment of the computer of the present invention;

Fig. 4 is a partly block, partly circuit diagram of two gating networks which are included in a gating matrix of the preferred embodiment of the invention shown in Fig. 1;

Figs. 5a through 5h are schematic circuit diagrams of a plurality of switches which are utilized in the computer of the present invention to initiate and control the various operations of the computer.

Referring now to the drawings, there is shown in Fig. l a complete, partly block, partly circuit diagram of a preferred embodiment of a magnetic drum, general purpose computer according to the present invention. As shown in Fig. l, the computer comprises the following basic components: A rotatable magnetic drum 21 with associated magnetic transducers and read-write circuitry for reading and writing signals on the surface of the drum; a first group of flip-flops designated L L L X X X Y Y;.,, W and M associated with the read and write circuitry; a second group of flipfiops designated D, K, S, R, Q, and P which constitute an instruction register; a third group of flip-flops designated C, B B 0 0 I and T, whose functions will be described; a gating matrix 20 which receives output signals from the flip-flops and applied resultant input signals to the flip-flops; and a control panel 22 including a plurality of control switches which are utilized for generating electrical signals (designated switch signals) for application to gating matrix 20 to initiate and control the various operations of the computer.

The periphery of drum 21 is provided with two separate counter-wound helical tracks, designated precincts 1 and 2 in Fig. l, which, together with a read fiip-flop W, and a write amplifier E constitute the main computer memory, hereinafter referred to as channel W. These tracks are traversed by two transducers 11a and 11b, respectively, which as indicated in Fig. l are moved together up and down in axially reciprocating motions synchronized with the rotation of drum 21. When the transducers are moving downward (as shown in the drawing), the helical track which constitutes precinct l is traversed by transducer 11a, While when they are moving upwards, the helical track which constitutes precinct 2 is traversed by transducer 11b. Each transducer is rendered operative (for reading or writing) only when it is traversing its corresponding precinct, this being accomplished by means of a toggle switch 30a which is actuated so as to connect transducer 11a to associated read-write circuitry when the transducers move down wards and to connect transducer 11b to this read-write circuitry when the transducers are moving upwards.

Another toggle switch 30b is actuated so as to generate a signal H having a high or low level in accordance with the precinct being traversed by the transducers. A signal H complementary to signal H is also generated, both signals being applied along corresponding conductors (designated conductor H and conductor H, respectively), to matrix 20 to thereby serve to identify the precinct being traversed. In the operation of toggle switch 30b, a source of relatively high potential V (not shown) is connected either to conductors H or H in accordance with the switch position, both conductors being otherwise held at relatively low voltage levels by voltage applied thereto through associated resistors 31 and 32 from a source (not shown) of relatively low potential V;,.

Referring now to Fig. 2 there is shown a developed view of one form of transducer moving mechanism which imparts the desired reciprocating motion to transducers 11a and 11b and actuates switches 30a and 30b in synchronism with rotation of drum 2 1. The mechanism includes two transducer mounts 35a and 35b for mounting transducers 11a and 11b respectively, the mounts being longitudinally slideable on a guide rod 36 and being longitudinally driveable in response to rotation of a level wind shaft 37 to whose grooves they are pinioned. The level wind shaft is in turn driven in synchronism with drum 21 through a suitable gear reduction unit generally designated 38. Toggle switches 30a and 30b are tandemly mounted on guide-rod 36 so that they are both thrown together to upper and lower positions respectively when the mounts 35a and 35b reach their corresponding upper and lower limit positions. In this manner the positions of the switche is made to correspond with the precincts being traversed.

Although this type of simple recognition by means of switches of the precinct being traversed is preferable, from the point of view of economy of equipment, it will be recognized numerous other forms of recognition means may be utilized. In addition, since the switches take a variable and relatively long time to change over, it is desirable, in order not to lose information, not to utilize those portions of precincts l and 2 whose traversals correspond to the time of occurrence of the switching operations. In the operation of the computer, the switching operations are so synchronized with respect to drum 21 that they occur near the ends of precincts l and 2, and, in particular, in the middle of those portions of the precincts as constitute blocks 33, as explained below. Information, therefore, is ordinarily neither read from nor written into either of the blocks 33 of channel W, this it has been found providing adequate protection against loss of information.

Considering briefly the read-write circuitry to which transducer 11a or 11b is selectively coupled via switch 30a, it is seen referring to Fig. 1 that the winding of the transducer selected by switch 30a is connected by a pair of conductors 51 and 52 to the output of a gated write amplifier E and is also coupled by a transformer generally designated 53 to the input of a read amplifier 54. Read Ll amplifier 54 is responsive to variations in current through the transducer winding for producing corresponding output signals SW and ZW which are applied to read flip-flop W to set or zero the flip-flop in accordance with the l or 0 values of signals passing beneath the read transducer.

Gated write amplifier E comprises a low impedance output amplifier generally designated 55 to which the transducer winding is connected and a conventional diode bridge gating circuit generally designated 56 which receives complementary gating signals Wr and Wr' and an input signal E applied thereto by matrix 20. Normally, when signal E is not to be recorded in channel W, the gating signals Wr and Wr' have low and high voltage levels respectively and in response thereto diode bridge 56 acts as an open circuit blocking passage of signal E to output amplifier 55. Amplifier 55 then functions merely as a passive low impedance path for the completion of current flow through the transducer winding. However when signal E is to be recorded or written into channel W, the gating signals Wr and Wr are maintained at their high and low levels respectively and in response thereto diode bridge 56 acts as a low impedance connection for applying signal E to amplifier 55 which amplifies the signal to produce corresponding current variations in the transducer winding, thereby writing or recording signal E in channel W.

Signals received by read amplifier 54 during the period in which writing is being performed are of too great an amplitude to be properly utilized by the amplifier and therefore any signals received by flip-flop W during this period and shortly thereafter cannot be used for any purpose. In addition, signals received by flip-flop W may be incorrect during the transducer switching operation. At other times the states of flip-flop W continuously represent the values of signals passing in the W channel beneath the selected transducer 11:: or 11b.

Referring again to Fig. 1, it is seen that in addition to channel W, drum 21 has five magnetizable tracks or hands designated 38, 39, 40, 41 and 42. In track 39, a timing signal waveform 0r so-called clock pulse waveform is permanently recorded, this waveform comprising in the present computer 2904 evenly spaced timing signals recorded about the periphery of the drum as successively adjacent regions or cells of the drum surface alternately magnetized in opposite directions of polarization. Upon rotation of drum 21, each passage of a timing signal beneath a read transducer 45, positioned adjacent track 39, causes the transducer to produce a corresponding electrical signal which is applied to a wave shaping circuit or clock pulse generator 46 which converts the signals to an output train of sharp electrical clock" pulses Cl. Each appearance of a clock pulse Cl indicates the passage of one of the magnetized timing cells of track 39 beneath transducer 45.

Clock pulses C1 are applied to matrix 20 and are utilized therein to synchronize almost all of the operations of the computer. Transitions in the electronic 1 or 0 states of the flip-flop circuits are made only upon the appearance of a clock pulse signal. Recording in magnetic form of bi-valued l or 0 signals upon all of the memory tracks (including the helical tracks of precincts l and 2) is synchronized with the clock pulses in such a manner that these tracks are effectively divided into discrete storage cells corresponding to the timing track cells.

For example, it is clear that each complete coil of the helical track of precinct l or 2 of the W channel will contain 2904 cells as demarked by clock pulses Cl. As pointed out below the W channel is intended to contain 66 blocks of 33 words each, each word having 84 cells, or a total of 182,952 cells. It can be seen, therefore, that the W channel comprises an integral number of coils, namely 63 coils so that precincts 1 and 2 will each comprise 31% coils. Because of this integral relationship between the effective length of the W channel and the effective length of the drum periphery, blocks stored in the W channel continually occupy the same positions on the surface of the drum and therefore the described transducer switching operations remain properly synchronized with the appearance of blocks 33 of precincts l and 2.

Track 40 cooperates with a write transducer 16 and a read transducer 17 to form a first recirculating channel, hereinafter referred to as the Y channel. The path of information flow of the Y channel is as follows: Read transducer 17, read flip-flop Y gating matrix 20, and write flip-flop Y As shown in Fig. l, flip-flops Y and Y; are coupled to their associated read and write transducers 17 and 16 through corresponding conventional read and write amplifiers.

In a similar manner, track 41 cooperates with a write transducer 14 and a read transducer 15 to form a second recirculating write channel, hereinafter referred to as the X channel. The path of information flow in the X channel is as follows: Read transducer 15, read fiip-flop X gating matrix 20, intermediate flip-flop X gating matrix 20, and write flip-flop X Finally, a third recirculating channel, hereinafter referred to as the L-B channel is maintained over that segment of track 42 moving between a write transducer 12 and a read transducer 13. The flipflops of the LB channel are read flip-flop L intermediate flip-flop L and write flip-flop L As shown in Fig. 1, permanent magnet erase heads 48, 49 and 50 may be positioned adjacent tracks 40, 41 and 42 respectively, for erasing stored signals after they have passed read transducer 17, 15 and 13 respectively, so that signals are returned to the Y, X and LB recirculating channels only through the corresponding write transducers 16, 14 and 12. It will be understood however that in many forms of magnetic recording the use of such erase heads is not required, the write transducers in their action overwriting any interfering signals.

In track 38 there is provided a special non-recirculating channel, hereinafter referred to as the M channel, wherein are permanently stored certain signals which, in an initial set-up operation called the mark operation, are copied into the X and L-B channels. The signals stored in track 38 are read by a read transducer 51 which is coupled through an associated read amplifier to a read flip-flop M, whose output signals are applied to gating matrix 20.

To clarify the nomenclature which will be utilized in connection with the flip-flops utilized in the computer, consider flip-flop M, as shown in Fig. l. Flip-flop M includes a pair of input conductors SM (Set M) and ZM (Zero M) and a pair of output conductors designated M and M, the designations of these input conductors corresponding to the designations of the signals applied along these conductors (as the SM and ZM signals and the M and M output signals). It will be understood that in response to selective application of an SM or ZM input signal the flip-flop will be accordingly set" to its 1 representing electrical state or zeroed to its representing electrical state. Simultaneous application of SM and ZM input signals will cause the flip-flop to trigger" or reverse its state. The electrical state of the fiip-flop (usually the current conduction of either one or the other of a pair of cross-coupled amplifiers within the flip-flop) is externally displayed by the voltage levels of its output signals, signal M having a high or low voltage level when flip-flop M is in its 1 or 0 states and signal M being complementary to signal M (so that signal M has low and high voltage levels respectively when flip-flop M is in its 1 and 0 states).

Corresponding nomenclature and operation will be understood to apply to each of the other flip-flops of the computer. For convenience in drawing virtually all of the flip-flop input and output signals and other signals are labeled at the points at which these signals emerge from or are applied to matrix 20 as shown in Fig. 1.

It will be understood that basically in the preferred embodiment of the computer shown in Fig. l virtually all operational processes are carried on by successive changes in the states of the computer flip-flops. At the end of each timing interval (as demarked by the appearance of a clock pulse Cl) each flip-flop is either set by application of a signal to its set (S) input conductor or zeroed by application of a signal to its zero (2) input conductor, or is possibly triggered by simultaneous application of signals to both its input conductors, or receives no input signals thereby maintaining its former state. The read flip-flops M, W, X Y and L, are each set or zeroed in accordance with the binary l or 0 values of magnetic signals then traversing beneath their associated read transducers. The remaining flip-flops receive their set (S) or zero (Z) input signals from gating matrix 20, which selectively generates these signals in accordance with the flip-flop output signals and other signals (the switch signals for example) received by matrix 20 during the previous timing interval.

In the structural description of the computer of the present invention, the general functions of only the first group of flip-flops has been presented thus far. consideration is now given to the general functions of the second and third groups of flip-flops.

As pointed out above, the second group of flip-flops, namely, flip-flops D, K, S, R, Q, and P constitute an instruction register. More particularly, these flip-flops normally operate as a serial shift register in which digit information contained in flip-flop L, of the L-B channel is shifted into flip-flop D and thence through the other flip-flops in the order designated, until the entire instruction is stored therein. As pointed out in more detail below, each instruction contains six digits, and, therefore, the instruction register contains six flip-flops.

The third group of fiip fiops is composed of flip-flops C, 3,, B 0,, O 0 I, and T. The general function of each of these flip-flops will now be considered briefly in the order given.

Flip-flop C is an operational control flip-flop and performs a number of functions during the various operations of the computer. For example, flipfiop C stores the successive carry digits during the mathematical operations of addition and subtraction. In addition, during the Test operation, described in detail below, flip-flop C temporarily stores the sign of the number formed in the X channel. The complete function of operational control flip-flop C, including the functions set forth above, are described in detail below in connection with the specific operations of the computer of this invention.

Flip-flops B and B are information transfer control flip-flops which operate to control the how of information between the L-B channel and the W channel. As set forth in greater detail below, the flow of information follows a predetermined pattern, hereinafter referred to as a block program, the elements of the pattern being determined by the states of flip-flops B and B Flip-flops O O and 0 are input information flipflops which operate to control the initial information inserted in the memory channels during the "mark and fill operations of the computer. For example, during mark, signals stored in the M channel are copied into the X and L-B channels under the control of these flipfiops. During fill, the flip-flops control the initial information loaded into the W channel and L-B channel.

Flip-flops I and T are identification or timing fiipflops which operate to identify the cells of the L-B channel. Flip-flop T changes state for each successive timing interval, as defined by clock pulses Cl, and, therefore, identifies alternate cells of the channel. The sequence of states of flip-flop I is set forth in detail below.

The remaining basic components of the computer shown in Fig. l are gating matrix 20 and control panel 22. As set forth above, gating matrix 20 receives the output signals of the flip-flops and electrical signals from the control panel, and generates input signals to the flipflops. More particularly, gating matrix 20 is composed of a plurality of combinations of and" and or" circuits, as determined by a plurality of logical equations, for generating, in synchronism with clock pulses Cl, a corresponding pluarlity of setting and zeroing signals for the flip-flops. The logical equations, and the manner in which the equations are mechanized by gating matrix 20, are set forth in detail below.

Control panel 22 includes a plurality of switches and buttons and means for generating electrical switch signals in response to the positions of the switches and buttons. More particularly, control panel 22 includes the following:

Power switch 70-for applying power to the computer.

Clear button 71-for clearing all prior information out of the computer.

Mark button 72-for inserting initial control signals into the computer.

Compute switch 73--for setting the computer into the compute phase and/or for filling initial conditions into the computer.

Fill buttons 75 and 76for operation with compute switch 73 to till 1 and digits respectively, into the alternate cells of the LB channel. Note, however, that for greatcr entry speed, buttons 75 and 76 may be replaced by punched tapes or similar entry means.

Oopy switch 78for operation with compute switch 73 to copy the information filled into each cell of the L-B channel into the immediately succeeding cell.

Write switch 79-for operation with compute switch 73 to write the copied information into the W channel; and

Start button Sit-for operation with compute switch 73 to initiate computation.

As shown in Fig. 1 control panel 22 generates a pinrality of signals which are applied to gating matrix 20. The manner in which these signals are generated will be described in detail below.

WORD STRUCTURE Reference is now made to Fig. 3 which is a diagram, hereinafter termed a word structure diagram, representing on a common time scale the contents of the successive cells of the Y, X, L-B and W channels, together with waveforms of signals C], I, and T for one cycle of the Y channel. Since the serially arranged digits of each channel. as shown in Fig. 3 will appear in the same order in the corresponding read flip-flops of the channels, the diagram of Fig. 3 also represents the successive contents of the read flip-flops during one cycle of the Y channel, as marked by clock pulse Cl.

As indicated in Fig. 3, each cell in each channel is magnetized in one sense or the other to represent a binary (l or 0) digit of information. A group of digits together constitute a word which is the primary unit of information in the computer and, in the embodiment shown in Fig. 3, comprises 42 digits.

Within a word the first 6 digits designate an instruction, the next 4 digits are so-called tabs whose function will be described later, and the last 32 digits will normally be the successive digits and sign of a binary number (although as described hereinbelow these digits may, alternately, represent the addresses in the memory of other words). Negative numbers may be held in the complemented form, the sign digit of a positive number being a l-valued signal and the sign digit of a negative number a O-valued signal.

Words are grouped into sets of 33 words, called blocks. In the specific computer described herein 66 blocks are held in the W channel, these being divided into 33 blocks per precinct. Words within a block are ordered-that is, they occur successively within the W channel, the successive words within a block being designated Word 1, Word 2 Word 33, or in abbreviated form W1, W2 W33. In a similar manner blocks are ordered within a precinct, the successive blocks within a precinct being designated Block 1 (Bl 1), Block 2 (Bi 2) Block 33 (BI 33), respectively.

The general organization of the words, blocks and sectors within the memory is diagrammatically illustrated in Fig. 3. At the time illustrated in Fig. 3, the last digit of the last word (W33) of the last block (Bl33) of the second precinct (Pr2) has just traversed past the read transducer of the W channel and the first digit of the first word (W1) of Block 1 Precinct 1 (Bll Prl) is now traversing beneath the transducer. In continuing opera tion all of the stored digits of Precinct 1 and then of Precinct 2 will pass serially beneath the read transducer of the W channel, one complete passage of all of these stored digits being designated a cycle of operation (or turn) of the W channel.

Reference is made first to the L-B channel shown in Fig. 3 for a more complete understanding of the word structure. It has been stated that a word in the present computer comprises 42 digits and that a block contains 33 words. Now the L-B channel holds two blocks of information, hereinafter referred to as the L block and the B block. Therefore, the number of digits in the LB channel is equal to 2(blocks) 33(words) 42(digits) or 2772 digits.

Although the digits and blocks in the L-B channel could be arranged in a number of ways, in the arrangement shown in Fig. 3, the L and B blocks are intcrplexed digit by digit along track 42. Thus, as shown in Fig. 3, the digits of the instruction portion of the first word of the B block, designated b through b are located in alternate cells of the L-B channel, the b digit traversing beneath the read transducer of the channel at the time the first digit of W1 is traversing beneath its read transducer. Similarly, the corresponding instruction digits of the first word of the L block, designated 1 through l are located in alternate cells, each 1 digit immediately following the corresponding b digit.

As set forth above, the four digits following the instruction digits of each word are tab digits, and, therefore, the next eight cells of the L-B channel are occu pied by the interplexed tabs of the B and L words. For purposes of simplicity of explanation, all of the tabs are shown in the first set of interplexed B and L words, it being understood that the tabs may not necessarily all appear as shown in Fig. 3.

The successive tabs of the B word are designated t t t,, and f, while the tabs of the L Word are designated t,, t and Of the latter group I is not utilized and (designated as the fiducial mark) appears only in Word 33 of the lr-B channel and is the unique and distinctive signal which identifies W33 as the last word of the L-B channel.

It is important for several reasons that W33 of the L-B channel be uniquely identified-first, because transi' tions between block programs must take place only during the passage of W33 (as it happens, upon the appearance of the fiducial mark) and secondly, because many of the tabs have an entirely different significance in W33 than they have in any of the other words of the L-B block. For example, as indicated by the legend, in Fig. 3, the t tab is normally a precessing signal which will be in W2 at the time illustrated and will be moved one word (to the left in Fig. 3) for each turn of the LB channel, skipping W33, to thereby identify the corresponding blocks in the W channel for purposes of block addressing. However in W33 the corresponding tab, designated if to distinguish it from the normal t tab, is used to designate the block program being performed, as will be shown hereinbelow.

As another example, the presence of the t tab in any W, of the L-B block normally positionally designates that BI, is the next block to be read from or written into the W channel. In W33 however, the corresponding tab designated t indicates the precinct (whether Prl or 2) of the selected block in the W channel. The functions of the tabs t,,, and 1,, in all words other than W33 relate in a manner to be described to the block addressing operations, while the corresponding tabs in W33 designated t t and 1,3 are used in connection with the identification of the precincts of selected blocks.

The remaining digits of the B and L words are designated b through b and S and through 1 and S As noted above, these digits normally represent the number and sign of the B and L words, respectively, and are also interplexed in alternate cells of the LB channel, as shown in Fig. 3.

It will be apparent that the L-B channel comprises not only the section of magnetic track lying between write transducer 12 and read transducer 13, but also flip-flops L L and L and the read and write circuitry. Since the output signals of a flip-flop are indicative of the signals stored therein, the fiip-flops L L and L may be thought of as windows through which three consecutive signals of the 2772 recirculating digit signals in the L-B channel may be viewed or sensed. In particular the signal passing beneath read transducer 13 will simultaneously appear in flip-flop L, the signal appearing in flip-flop L will be written simultaneously by write transducer 13, and the signal immediately preceding b in L will appear in flip-flop L as shown in Fig. 3. Accordingly, of the 2772 digits of the L-B channel, one digit will always be stored in fiip-flop L and the remaining digits on track 42.

Referring next to the W channel, it has been stated that each word of this channel contains 84 cells. On the other hand, it has been stated that each word includes only 42 digits, one-half the number of cells of a word in the W channel. The reason for the difference is that the digits of a word in the W channel are located in alternate cells in order to correspond to the digits in the L-B channel, as shown in Fig. 3. Stated difl erently, since the L-B channel contains 2772 cells and one block of channel W contains 33(words) X84(cells), one complete circulation of the information contained in the L-B channel (hereinafter termed one turn of the channel) corresponds to the time required for one block of information in the W channel to pass beneath its read transducer.

As shown in Fig. 3 the digits of the words of the W block appear in read flip-flop W at times T (at times when signal T is at its high level). Since the digits of the B block of the LB channel also appear in read flipfiop L at these times, the words in the W channel are considered as belonging to B blocks and are so designated in the W channel. The reason for this arrangement is discussed below in connection with the section on information flow.

Only a single tab, t is shown in Fig. 3 for the reason that, although other tabs are recorded in the W channel, only the t tab (and the corresponding 1,,* tab) is read back from the channel. Thus since only this 1,, tab (and the 1,,* tab) has significance in the words of the W channel, it alone is shown in Fig. 3.

From a consideration of the W channel it is clear that there is space therein for an additional equal number of blocks which might be interplexed with those already present. Those skilled in the art will readily perceive how through relatively simple modifications of the present computer, facilities may be provided for addressing to and from such additional blocks.

The next channel to be considered is the X channel which, as shown in Fig. 3 contains 84 cells and has a cycle of operation corresponding to the passage of a 14 single word in the W channel beneath its read trans: ducer. As in the LB channel, one of the digits stored in the X channel is contained in flip-flop X while the remaining 83 digit signals appear in track 41. In order to permit ready comparison of the digit information in the various channels, the digits actually stored in flipflops X and X are also shown in dotted outline at the end of the X channel in Fig. 3.

It has been stated previously that the X channel contains an X number, the digits and sign of which are designated X X X and 8, respectively. As shown in Fig. 3 the digits of the X number occupy the same relative positions in the X channel as the corresponding digits of the L number in the then appearing word of the LB channel, with zero-valued signals being stored in the immediately preceding cells. It will be shown below that this arrangement greatly simplifies the performance of serial operations upon the two numbers X and L.

All but the first of the cells of the X channel corresponding to the instruction digits of the LB channel and the cell corresponding to tab t of the L-B channel are filled with zero-valued signals, as shown in Fig. 3. On the other hand, certain cells are filled with one-valued signals and are designated m n m m and n in the order of their appearance in the X channel. The cell preceding m contains a signal t and the cell preceding m contains a signal v, both of which will be discussed below. The zero and one-valued signals shown in the X channel are normally recirculated without change in the operations of the computer.

The primary purpose of the marks stored in the X channel is to identify particular cells in the words of the L-B channel; that is, the appearance of the marks in flip-flops X X and X distinguish the times of appearance of corresponding signals of the L word in flip-flops L L and L The signals I and T (and I and T) are used in conjunction with the marks for this purpose. The manner in which the times of appearance of particular signals of an L-B word are identified by signals I, T and the marks in the X channel is best illustrated by a few examples.

Suppose that it is desired to distinguish the time at which fiducial mark may appear in flip-flop L At that time, as shown in Fig. 3, signal I, which is at a low level during the time intervals corresponding to digits b through f of the LFB channel and a high value at all other times, will be low, and signal I which is the complement of I will be high. At the same time, signal T, which is at a high level of all L digits and a low level on all B digits, as shown in Fig. 3, will be high. The m mark will be in flip-flop X (so that signal X will be high). Thus, the time at which the fiducial mark may appear in L will always be the unique condition indicated by signals I an d T 3% X all being at their high levels, this being expressed by the Boolean expression I'TX Similar expressions may be provided to illustrate the identification of the times of appearance of other signals. For example, listing some of these:

The time at which tab t may appear in flip-flop L is distinguished by the unique condition of signal 1' high, signal T high, and 11 mark in X and a O-valued signal in X hence by I'TX X The time at which tab t may appear in flip-flop L is distinguished by the unique condition I'TX X' The time at which tab t, may appear in flip-flop L is also distinguished by I'T'X X' and The times of appearance of digits 1,, 1 through 1 and S in flip-flop L are distinguished by ITX In the same manner all required identifications of the appearance of particular signals or groupings of signals in the flip-flops of the L-B channel (or in the flip-flops of the X, Y and W channels) may be similarly accomplished.

The last channel shown in Fig. 3 is the Y channel which contains 86 cells, that is two more cells than the X channel. As a result, signals stored in the Y channel will be delayed or precessed with respect to corresponding signals appearing in the X and L-B channels. More particularly, each signal initially stored in the Y channel will thereafter precess two cells to the left, as viewed in Fig. 3, relative to the corresponding signals in the X and L-B channels. For example, signal 11,, which is shown in Fig. 3 as being aligned with signal X of the X channel and signal 1 of the first L word of the L B channel, will be aligned with signal X of the X channel and signal 1 of the second L word of the L-B channel during the next turn of the X channel.

As shown in Fig. 3, the Y channel has provision for storing two numbers Y and P. The digits and sign of Y, namely y, through y and s,,, are shown in Fig. 3 as being aligned with the B word of the L-B channel, while the digits p, through p and sign S of P are aligned with the corresponding digits of the L word of the L-B channel.

The described precession of digits in the Y channel with respect to digits in the L-B channel is utilized in the word addressing operations of the computer, as explained fully below. Those skilled in the art will also perceive how readily applicable such precession may be in the performance of such operations as multiplication where successive digits of a multiplier number may be stored in the Y channel so as to serially appear at predetermined times for operation upon a multiplicand number held in the Y channel.

BASIC PROCESSES OF THE COMPUTER The general purpose computer of the present invention simultaneously performs two basic processes, namely, a computation process in which computations are performed upon the L words in the L-B channel, and an information fiow process in which blocks are transferred between the W channel and the L-B channel. Generally speaking, each of these processes, and particularly the sequencing thereof, is carried on independently of the other. It should be apparent, however, that there is a definite relationship between the processes, and this relationship will become clear from the detailed description of the computer. For the purpose of clarity of the present description, each of the basic processes will now be considered separately.

(a) Computation process In the computing process of the computer, computations are normally performed upon the numbers of the L words in the L-B channel and the number in the X channel. More particularly, the words in the L block are treated serially, so that first the instruction and number of Word 1 (Wl) of the L block are operated upon, then the instruction and number of Word 2 (W2) of the L block and so on. Ordinarily an instruction in a word will designate a mathematical operation to be performed upon the immediately succeeding number of the same word. For example tht appearance of an addition instruction, 001000. in the first six cells of L word causes the succeeding number of the same L word to be added to the X number in the X channel. The addition operation is completed during the passage of the L word through the L L and L flip-flops so that when the L word has completed its passage, the computer will be ready to accept the instruction contained in the next L word and operate in accordance therewith upon the number contained in this word.

Such operations which are performed within the passage of a single word are called one-pass operations. However even if an instruction in a word orders an operation which cannot be performed within the passage of a single word (a so-called multi-pass operation), the described serial mode of operation may still be preserved-that is the next instruction accepted will be the instruction in the next word. When an L word instruction ordering such a rnulti-pass operation occurs, a signal, designated a flag tab, is stored in the fourth or f tab position of the corresponding interplexed B word, as shown in Fig. 3, to thereafter identify the word in which this initiating instruction occurred. After the performance of the multi-pass operation, which may require one or several turns of the LB channel, serial operation is continued by recognizing (and removing) the flag tab and then accepting the instruction in the next word following the flag tab. The manner in which the computer recognizes and removes the f tab is explained in detail below.

It is seen that in the described purely serial mode of operation upon the successive words of the 1.43 block, addressing operations will not ordinarily be required, the sequence in which mathematical operations are performed being determined by the sequence in which words (and their corresponding instructions) are stored in the memory. This might be described as being essentially no-address operation upon the words of the L block.

However it will be understood by those skilled in the art, that it is sometimes desirable to disrupt such purely serial operation, as for example in response to a so-called jump instruction, as explained more fully below, to skip over one or a group of words to a remote word. When such an L word jump instruction occurs, it signifies that the digits in the number part of the same word do not designate a quantity but instead designate the address or position in the L-B channel of the desired remote word. More particularly, the address or position of the remote word relative to the instruction word is designated by the position of a single signal stored within one of the 32 cells of the number part of the word.

The particular addressing method set forth above, in which each address is designated by the position of a single signal in one of the 32 cells of the number portion of a word, has an additional advantage in that a plurality of addresses (up to 32 arbitrarily selected addresses) can be designated in the number portion of a single word by appropriately positioning therein a corresponding plurality of signals. This feature of the present computer is utilized in connection with so-called Put instructions, that is Put in L (PI) and Put in B (Pb).

In response to the occurrence of a PI instruction in a word of the L block, the X number in the X channel is copied into the number portion of certain words in the L block, as arbitrarily designated by corresponding signals stored in corresponding cells of the number portion of the word containing the Pl instruction. A Pb (Put in B) instruction is also available. The use of these unique instructions greatly facilitates the programming of complex mathematical problems.

The manner in which a signal stored in an appropriate cell of the number portion of a word carrying a put or jump instruction can act to identify a corresponding remote word will be described in detail at a later point in the present specification. It may be stated briefly however that what is done is to copy such a signal, as it appears in flip-flop L; of the L-B channel, into a simultaneously appearing cell of the Y channel, that is to transfer the signal from flip-flop L to flip-flop Y Since the Y channel is two cells longer than a word of the L-B channel, as stated before, a signal stored in the Y channel will precess 2 cells (counterclockwise, as shown in Fig. 3) for each passage of a word in the L-B channel. Eventually as a result of such precession, the stored signal will emerge in the Y channel (appearing in flipflop Y of the Y channel) at the same time that the first digit of a word emerges in the L-B channel. This coincidental appearance of the stored signal and the digit at the front of an emerging word is recognized, and the emerging word is thereby identified as the desired remote word.

As an example, if a jump instruction in a word is intended to cause a jump to the third word therefrom (so that the instruction of the Wild word will be accepted) then a signal will be stored in the third last cell (the cell which normally contains the Z digit) of the number portion of the word in which the jump instruction appears. Similarly a jump from a word containing a jump instruction to the fifteenth word therefrom, would be indicated by a signal stored in the fifteenth last cell (the cell which normally contains the Z digit) of the number portion of the jump instruction containing word. In the general case a jump or put from any word W; to a remote W (where k may be positive or negative), is designated by a signal stored in the number portion of W in the 1334: position for positive k and in the L position for negative k. In this connection, it should be noted that the position is the S position shown in Fig. 3.

In summary, in a conventional single address computer, each word contains an address portion which in each instance designates where the next numbtr to be operated upon is to be found. It is seen, that in contrast thereto, in the computer of the present invention, each word contains a number portion which alternatively designates either a number which is to be immediately operated upon in accordance with an accompanying instruction in the word, or the address of the next number which is to be utilized. The described mode of operation of the computer of the present invention insofar as word addressing is concerned is therefore called half-address op eration to distinguish it both from conventional singleaddress and from pure no-address operation.

(1)) Information flow process As stated before, computation operations are normally performed upon (and addressing operations made between) the words of the L block. In ordinary operation,

L blocks originate as blocks in the W channel which are brought up via read flip-flop W into the L-B channel. are computed upon, and are then returned to their positions in the W channel. A block brought up from the W channel to the L-B channel serves first, usually in a standby capacity, as a B block; then as an L block which is operated upon, then again as a B block, this time waiting to be written back into its position in the main memory; and finaliy is written back into the main memory when its position in the main memory passes beneath one of transducers 11a and 11b.

The normal procedure is as follows: When all computation upon an L block has been completed, the information in the L and B blocks are exchanged, a relatively simple operation to perform since the two blocks are interplexed digit by digit. White computations are being performed upon the new L block (the former B block), 55 the new B block (which is, of course, the former L block) is written back into its original position in the main memory. Thereafter while operation continues upon the L block, its successor block is read from the main channel to serve as the next B block.

The described manipulations of the blocks of the computer may be thought of as being divided into five block programs of the computer. These five block programs are designated, in the normal order of their occurrence as:

(1) Writethe B block is written into its position in the W channel.

(2) Readlmmediately follows Write, the next B block being read from the W channel.

(3) Preexchange-The period between Read and the 70 acceptance of an exchange (X) instwction in W33 of the L block which causes the transition from Preexchange to:

(4) Exchange-The information in the L and B blocks are interchanged.

(5) Postexchange-Tl1e period between Exchange and Write, this is the period between Exchange and the appearance in the W channel of the position to which the B block is to be returned.

It should be understood, however, that various deviations may occur in the normal order of occurrence of the block programs. Each of these durations will be described in detail below.

It has been previously stated that flip-flops B, and B have supervisory control over the performance of the block programs. Actually, the transition from one block program to another is controlled not only by these flipflops but by the value of the signal stored in the third or 1,, tab in W33 of the B word of the L-B channel, as shown in Fig. 3, this signal being designated 1,,* since it occurs in the fiducial word. The following table, Table 1. summarizes the relationship between each block program and the succeeding program, as determined by the value of t,*.

TABLE 1 From- To- States Value States Block ofof 1. Block of- Program Program B, B, B B

1 0 0 Read 1 1 1 1 0 Rea 1 l Rea 1 l 1 Preexchange. 0 0 Prcexchangc- 0 0 (1) Exchange 0 1 Exchange. t 0 1 0 Postexchange D 0 Postexchange. 0 0 0 Write 1 0 Exchange 0 1 1 Preexchange. 0 0

Lines (1) through (6) represent the normal sequence of the block programs, as set forth above. In this connection, it should be noted that in line (2) the read program continues until signal 1 has a value of 1, that is blocks from the W channel will be written into the B blocks of the L-B channel, one over the other, until the correct block is read. At this point the block program will transfer from Read to Preexchange, as indicated by line (3).

The significance of the parentheses in the t,,* column of line (4) will now be considered. As indicated in line (4), Preexchange normally transfers to Exchange if signal 23* has a value of 1. There is one further condition for this transition, namely, that an Exchange instruetion in W33 be accepted. As pointed out in detail below, there are several circumstances under which this condition is not met. Under these circumstances, the computer of the present invention will remain in the Preexchange program.

Line (7) of Table 1 represents a variation from the normal block program sequence when the computer is in the Exchange program. As indicated, if signal t has a value of 1, instead of 0 as in line (5), the transition will be from Exchange back to Prcexchange. This condition occurs when Exchange instructions are accepted from both W32 and W33. The significance of the variation will be set forth below in connection with the list of instructions.

The manner in which the computer identifies the position in the W channel from which a block is to be read or into which it is to be written, will now be considered. In each instance the block number of the position in the W channel from which a block is to be read (or Written into) is positionally designated by the presence of a single signal stored in the second t tab cell of a correspondingly numbered word of the L block, as shown in Fig. 3. The precinct number (whether Prl or 2) of the desired block position is indicated by the value (whether or 1, respectively), of a signal, stored in the second or 1 tab cell of the last or fiducial word, W33 of the L block.

As an example of this system of addressing to block positions in the W channel, assume that a B block is to be written into Block 2, Precinct 1 (BIZ-Prl) of the W channel. To designate this position, the t tab will be stored in the correspondingly numbered word, W2, of the L block, and the t tab in W33 of the L block will have the value 0.

The manner in which these tabs are actually used to identify desired block positions will be described in detail at a later point in this specification. However it can be briefly explained at this point that what is done is to provide in a unique manner, information as to the block number and precinct of the blocks passing beneath transducers 11a and 11b, so that reading or writing can be initiated when this information agrees with the address information supplied by the t and t tabs.

It will be recalled that information as to the precinct passing beneath the W channel transducer is supplied by switch 30b. In particular, switch 30b produces signal H (and complementary signal H) having a low level when Precinct 1 is being traversed and a high level when Precinct 2 is being traversed.

Information as to the numbers of the blocks passing beneath the active transducer of the W channel is provided by a precessing signal Which appears in the third or t tab cell of only one word of the B block and is moved left from word to word of the L-B block as viewed in Fig. 3. The t,, tab is moved one Word for each turn of the L-B channel, so that in operation the 1,, tab moves one word of the L-B block for each passage of a block in the W channel. In the present computer the t, tab is initially inserted so that it appears in W3 of the L-B channel when B12 of the W channel begins its passage. Thereafter the position of the I, tab remains as an ab solute reference to the blocks passing beneath the active transducer in the W channel, indicating the number of the block which will next appear in this channel.

The manner in which tab 2,, is in operation precessed one word for each complete turn of the LB channel may readily be explained with the aid of Fig. 3. During each passage of a word (other than W33) in the L-B channel signal t in the X channel and the signal representing tab t,, in the L-B channel are interchanged. Since tab t will be actually present in only one of the 33 words of the L-B channel, the described tab interchange operation will have the etIect when that word appears of removing the t,, tab from the word and placing the tab in the X channel. During the passage of the next word of the L-B channel the repetition of the tab interchange will have the effect of redepositing the 1 tab from the X channel into this next word of the L-B channel. In this manner, the 1,, tab is moved back one word of the L-B channel for each complete turn of the L-B channel.

It will be recalled that in W33 of the L-B channel, the t,,* tab is utilized in connection with block program transitions and its value controls the transition in cooperation with the states of flip-flops B and B For this reason, the t -z interchange is suppressed during passage of W33 of the thirty-first turn of the L-B channel, and, therefore, tab 1,, which was inserted in t during that turn will remain in the X channel. During passage of the next word of the L-B channel (W1 of the thirty-second turn) r -t, interchange occurs and tab t, is inserted in WI. Accordingly, on the next or thirtythird turn of the L-B channel, the tab z appears in W1 and is transferred to W2. In this way the tab stays in synchronism with the blocks of the W channel for utilization in the block addressing operations and yet avoids interference with the t,,* tab.

Interchange of the signals representing t and I, is

accomplished immediately after these signals appear in flip-flops X and L respectively. In the next timing interval, the signal in flip-flop X is placed in flip-flop L and the signal in flip-flop L is placed in flip-flop X thus accomplishing the desired t,,t,, interchange. Suppression of the t t interchange in W33 is accomplished through recognition of the presence of the fiducial mark in flip-flop L As an example of tab recognition assume that the 1,, tab is located in W2 of the L-B channel as Bil-Prl begins its passage in the W channel, as shown in Fig. 3. If, as was assumed before, the B block is to be written back into BIZ-Prl, then the t tab will also appear in W2 of the L-B channel, as was hereinbeforc explained. Therefore as W2 of the L-B channel appears, the coincidental appearance of the t, and t tabs in this Word may be recognized and will indicate that the next block (BIZ-Prl) to appear, in the W channel is that one (assuming its precinct is proper) into which the B block is to be written. The computer makes note of this coincidence of the t,, and I tabs (as will be seen), by inserting a signal in the v space of the X channel, as shown in Fig. 3.

The computer then waits, insofar as the block programs are concerned, until the last word, W33, of the L-B block appears so that the desired precinct (as indicated by the 1 tab in W33) may be verified against the true precinct of the next appearing block. B12 (as indicated by signal H). If precinct verification is obtained (and the v signal appears in the X channel) then it is known that the immediatel y succeeding W channel block is the proper one, the write program is entered in accordance with Table 1 and writing of the B block into this block is immediately initiated. If precinct verification were not obtained (as would be the case if the B block were to be returned to Pr2 rather than Prl) Postexchange program continues and the v signal is erased on the next turn of the L-B channel. The v signal would not be reinserted until I, and t tab coincidence was again obtained in W2 of the L-B channel, this time during passage of Bll-Pr2 of the W channel. All of the operations will then be repeated, concluding with the writing away of the B block into the proper block, B12, of P12 rather than Prl.

The addressing and recognition of blocks in the W channel for the purpose of reading such blocks into the L-B channel as B blocks is conducted in substantially the same manner. In the read program, however, the digit in v of the X channel has the opposite significance to that in the write program. The details of the read program are explained below.

It should be noted in connection with the block programs (Write, Read, Preexchange, Exchange, Postexchange) that for the most part the successive perf0rm ance of these programs is a semi-autonomous function of the computer carried on automatically, and independent of the ordinary computational operations performed upon the words of the L block. Thus for example computation on the L block may continue uninterruptedly throughout Write, Read and other block programs, saving considerable amounts of time.

INSTRUCTION LIST To further illustrate other distinctive features and capabilities of the computer of the present invention, and to clarify and further illustrate its operation, there is provided below a list of instructions which the specific computer to be described will respond to. Each instruction is designated first by an alphabetical abbreviation, then in parentheses by a verbal name if one existsfollowed by the six binary digits, most significant digit first, which designate the instruction and then by a statement as to the operations performed by the computer in response to the instruction.

A -(Add)O0l000-This L number is added to the X number and the sum is written into the X channel as the new X number.

S (Subtract)--001001The L number is subtracted from the X number and the dilference is written into the X channel as the new X number.

T -(Test)ll0lSame as A The sign of the sum is read and if the sum is negative the instruction in the next word is not read, computation beginning again with the word after that.

T (Test )001ll]Same as S The sign of the difference is read and if the difference is negative the instruction in the next word is not accepted.

Idle-O10000-This instruction stops all computation and simply allows recirculation without change of all memory channels.

Pas -000000If a word is not used its instruction digits are all left zero, this being designated as the Pass instruction. A word containing a Pass instruction will be ignored, computation beginning again at the next word.

W (Wait)-110010This instruction stops all computation until the block program Preexchange is entered. The f flag is left in the word containing the Wait instruction and computation recommences at the word following the flag.

U -(Unconditional transfer or jump)--lllOO0-This information transfers the point of computation to another word within the L block. As set forth above, if the word containing the U instruction is W and it is desired to transfer or jump to W the non-zero digit in the W, number will be l if k is positive and l-k if k is negative.

PI -(Put in L)1l11l0This instruction puts the X number into one or more words of the L block. As set forth above, the non-zero digit or digits are determined by the rule outlined above in connection with U Pb (Put in B)-llll}l0-This instruction in an L word puts the X number into a word or words of the B block. Pb differs from P1 in the transfer to the B block rather than the L block, as determined by the digits in the instruction. Pb is not accepted until the computer is in the Preexchange program.

Tl Take from L)-1l110l-This instruction moves the number of a designated L word into the X channel. The number following T1 is determined in the same way as that following Pl Th -{Take from B)-l110ll-This instruction moves the number of a designated B word into the X channel. The number following Tb is determined in the same way as that following Pb Tb is not accepted until the computer is in the Preexchange program.

X(Exchange)0ll0lI-This instruction causes the interchange of the L and B blocks, and is not accepted until the computer is in the Preexchange program. If the instruction appears in only W33 of the L block, the computer will enter its Exchange block program after this instruction has been accepted. The L and 13 blocks will then be interchanged, and thereafter the block program Postexchange will be initiated, as indicated in Table 1.

If however the X instruction is placed in W32 as well as W33, and (as a result of Test, for example) W32 is used, the Exchange block program will still be entered but will be followed by the block program Preexchange, as set forth above in connection with Table 1. This latter usage permits the L and B blocks to be computed upon consecutively as long as desired, until when (as a result of Test) W32 is skipped and only the X instruction in W33 is utilized. Then Exchange will be followed by the normal Postexchange and the normal block cycle will be resumed.

Br -(Branch)-ll100l--This instruction alters the normal block program sequence to permit a block from the W channel to be read in as the new B block in the L-B channel after the normal read program has been completed, the new B block being written over the pre- 22 viously read B block. The Br instruction is placed in a word in the L block which immediately follows an L word containing a test instruction, and it not accepted until the computer is in the Preexchange program.

As an illustration assume that in response to a test instruction in word W of the L block, the computer is required to read block B; if the test instruction is not satisfied and block B if the test instruction is satisfied. Assume that the computer has followed the normal block program squence and that block B has been read into the L--B channel in accordance with the normal t tab in W of the L block, as set forth above. Under these conditions the computer is in the Preexchange program so that the Br instruction may be accepted.

W of the L block, therefore, contains the Br instruction and a non-zero digit in the number portion designating the address of the W in accordance with the rules set forth above in connection with the U instruction. If the test instruction is not satisfied, the Br instruction is not accepted, in accordance with the rules set forth above for T and T and the B, block in the L-B channel is undisturbed.

If the test instruction is satisfied, the computer accepts the Br instruction in word W and performs the following operations. The t tab in W; is erased and a one valued signal is inserted in the f tab of this word. A new t tab is inserted in word W in accordance with the block addressing technique, to thereby identify the B block to be read. At the time block B begins its passage in the W channel, the computer program is changed from Preexchange to the phase of Read shown in line (3) of Table 1, thereby permitting block B to be read into the L-B channel as the new B block.

Upon the appearance of the f tab during the Read program, the Br instruction in the instruction register is removed and the f tab is erased. Computation begins again in word W in accordance with the instruction in that word, the normal block programming cycle combining in the manner previously described.

Start tape-This instruction orders the acceleration of an associated magnetic tape to full speed, so that the tape will have sufficient velocity for proper recording of readout information supplied by the computer.

Stop tape-This instruction orders the deceleration and stoppage of the associated magnetic tape, and is used to conserve tape after read-out operations have been completed.

Read-out-This instruction in a word signifies that the number portion of the same word is to be read out into the magnetic tape.

CLEAR, MARK AND FILL Before proceeding further with description of the computations performed by the computer, a brief explanation will be provided of the manner in which the computer of the present invention is placed in operation. It will be understood that in placing the computer in operation for a problem solution, first, any old information relating to former problems is removed or cleared from the recirculation channels of the computer; then, the required marks and the processing t tab are recorded in the X and L-B channels (this being designated the mark operation); and finally all of the required blocks of information are recorded in the W and L-B channels. These clear, mark, and fill operations may be performed by an operator through utilization of the control switches provided on control panel 22, as shown in Fig. 1.

The first step performed by an operator in placing the computer in operation is to throw main power switch 70, thereby supplying electrical power to the computer, and then to momentarily depress the clear button 71, thereby placing flip-flop Q in its 1 state and all other computer flip-flops in their 0 states. Write flip-flops Y X and 1. then record 0-valued signals in all of the cells of the 23 corresponding channels thus removing any unusable information contained therein.

Next, button 72 is momentarily depressed causing recording from the M channel of the fiducial mark and tab t,,* in the L-B channel thereby defining W33, and then of marks m 11 m m,,, it; and of signal i in the X channel. The recording of these signals is synchronized with the head-switching operation, the recording commencing at a predetermined time after signal H changes from its high to low level. The normal t -r, interchange operation immediately begins and is thereby properly related to the passage of blocks in the W channel, as explained in detail below.

The computer may then be filled with desired information blocks. In filling the computer, the normal path for a block of information is that first it is filled into the L block; next, it is copied from the L block into the B block; and then, it is written from the B block into its appropriate position in the main memory W channel. The second last block to be filled into the computer is not immediately written into the W channel but is retained in the LB channel as a B block. The last block filled in the computer is retained in the L-B channel as an L block. Computation is then started (with the computer in its Preexchange block program) upon the retained blocks held in the L-B channel. All of these operations may be controlled by an operator through utilization of the remaining switches provided on control panel 22.

In filling a block of information into the L block, after fill-compute toggle switch 73 has been thrown to its lower fill position, the successive land O-valued signals of a block may be entered into the L block by selectively depressing switches 75 and 76, respectively. Each signal entered by the switches is recorded in the first L or 1,, cell following the fiducial mark in W33 and is shifted two cells to the left, as viewed in Fig. 1, during entry of each subsequent signal. In this manner, all of the cells of the L block are filled with an information block.

The next step to be performed in fill is to cause the information in the L block to be copied into the B block. For this purpose, copy switch 78 is depressed and, in response thereto, the signals recorded in the L block cells are copied into the corresponding cells of the B block. Following this, write switch 79 is depressed, forcing the computer into its Write program so that the copied B block is written into its proper position (as designated by a t address tab carried within the block) in the W channel.

After Write has been completed the computer enters its Preexchange program, and is ready to have another block filled therein. Through repetition of the described operations, all of the required blocks of information are entered in the W channel. In entering the last two information blocks, write switch 79 is not utilized so that these blocks are retained in the L-B channel as L and B blocks. At this point, fill is completed and switch 73 is returned to its compute" position.

It should be noted that all flip-flops but flip-flop Q of the instruction register flip-flops P, Q, R, S, K, D are zeroed (as was accomplished by the clear operation), the states of these flip-flops corresponds to receipt of an Idle instruction, and further instructions will not be accepted, computation thus being stopped. The depression of start button 80 causes flip-flop Q to be zeroed at the next appearance of the fiducial mark, thereby removing the Idle instruction from the instruction register flip-flops and allowing L word instructions to be accepted by the instruction register.

EXAMPLE OF BLOCK ADDRESSING (The Tab System) When a block is filled into the computer it is normally filled into the L block so that it contains both its own address and the address of its successor block. The

24 blocks own address is filled therein so that the block can be initially filled into its proper position in the W channel. The address of the successor block is contained therein so that when the block is later computed upon (as an L block) it will be able to designate the next block to be read from the W channel.

In initially filling an information block into the L block, the block number of its own address is inserted therein as the position of the t tab and the block number of the address of its successor block is inserted therein as the position of the t tab. The precincts of its own and the successor blocks addresses are indicated in W33 of the L block as the values of the t and t,* tabs, respectively.

When such a block, is copied into the B block during the fill operation, the t and t (and t and 11*) tabs are copied into the r and t tabs (and t,,,* and t,,* tabs), respectively. The B block is then written away into its place in the W channel in accordance with the address specified by the t tab in the L block. Once the block is written into the W channel, only the t tab (and the t tab) retains significance (since reading of the other tabs will be suppressed in later operations). Therefore, it is clear that a block stored in the W channel effectively contains only the address of its successor block, this address being indicated by the position of the t tab (and the value of t tab).

The basic problem solved by the tab system is to manipulate these t and t,,* tabs so that during computation they serve at the proper times as I and t tabs to control the reading of successor blocks and also to control the return of blocks to their own W channel posi tions. In the following discussion of these manipulations, the tabs in W33 (t,,*, t,,*, tf" and t,,*) will not be separately referred to, for the manipulations to be described are commonly performed on both sets of tabs.

The last two blocks filled into the computer (those which will be retained as L and B blocks and with which computation will begin) are exceptional in that each carries the address of the other (rather than its own address) and also, as usual, the address of its successor block. After computation has begun, the repetition, during each cycle of the block programs, of the following two operations accomplishes all required manipulations of the tabs:

(1) During Exchange the signals in the t and t tabs are interchanged in each word of the L-B channel and also the signals in the t and 1,, tabs are interchanged.

(2) During Write, the signal in the t, tab is copied into the t tab in each word of the L-B channel.

The described manipulation of the tabs during fill and compute operations and also the sequence of operation in the block programs will be greatly clarified by consideration of an illustrative example. Assume for the purposes of this example, that it is desired that computation begin upon B11 and that Bil is to he succeeded by B12, which is to he succeeded in turn by B13, then by B14, and so forth. To accomplish this, Bll will be the last block filled into the computer (so that it serves as an initial L block) and B12 will be the second last block filled therein (so that it will serve as the initial B block).

The following table, Table 2 indicates the placement of the tabs within the words of the LB channel during successive fill operations and compute programs, beginning with the filling of B12 into the L block of the L-B channel. In Table 2, the solid horizontal line demarks the boundary between the fill operations and the succeeding compute block programs and the dashed horizonal lines demark four successive full cycles of the block programs. The various fill operations and block programs are numbered as entries 1-23 in the order of their occurrence to facilitate discussion thereof. For purposes of clarification, the corresponding states of the block program control flip-flops B and B and also the values of the t,,* tab are shown in Table 2.

TABLE 2 States of Words of L-B channel in which are positioned Entry Fill Operations and Compute the Tabs Block Programs 1 1 is o v 31 lb 0 1 Fill B12 into L block 3 0 0 1 Copy 1- 1 3-3 0 D 1 F11 Bll into L block... 2 1-'2 3 0 D 1 Precxchange 2 1 2 3 0 1 0 Exchange (B11 and B12) c. 1H2 3 2 0 0 0 Postexchange 1 2 3 2 1 0 0 Write (B11 into W channel) 3 2 3 2 l 1 0 1 Read (Bl3) 3 2 3 4 0 l) 1 Preexehange 3 2 3 4 D 1 0 Exchange (B12 and B13) 2 t3 I -)3 0 0 0 Postexchange 2 3 4 l l 0 0 Write (B12 to W channel) 4 3 -4 3 1 1 Del Read (1314) c 4 3 4 0 0 1 Precxchangc 4 3 4 5 0 l 0 Exchange (Bl3 and 1314).. 3-+4 [S 4 O 0 0 Postcxchangc 3 4 5 4 l D 0 Write (B13 into W channel) 5+- 4 -S 4 1 l ll-vl Read (1315) n 5 4 5 64 0 0 1 Preexchangc 5 4 5 6 0 l 0 Exchange (B14 and B15) 4H5 SS5 0 0 0 Postexchange 4 5 b 5 1 O 0 Write (B14 into W channel) 6 5 in 5 1 l 0 l Read (B16) 6 5 6 7 1) In entry 1 of Table 2, it is seen that when B12 tify the address in the W channel to which the B block is filled into the L block of the L-B channel, it carries the (B11) is to be returned in a succeeding Write program. address of B11 as the t tab (entered into W1) and the The identification is accomplished by looking for t address of its successor block (B13) as the t tab (entered tab coincidence (coincidental appearance of t,, and i in into W3). 85 the same word), such tab coincidence during a turn of (2) In entry 2, B12 is copied into the B block of the the L4) channel indicating that the correct block (as- LB channel, thereby copying the t and t; tabs (as indisuming its pr is p p Will appear in the W cated by the arrows) into the t and t tabs, respectively. channel during the next turn of the L-B channel.

(3) In entry 3, it is seen that when B11 is filled into When tab coincidence occurs (in WI in the present the L block of the L-B channel, it carries the address of example) dur ng a tu n f the L43 Channel, it is K181110- BI2 as the t tab (entered into W2) and the dd f rized for the remainder of the turn by setting signal v in its successor block (also B12) as the 21 tab (entered the X channel to its 1valuc(v= Al the mp i n into W2). of the turn, upon the appearance of the fiducial mark The fill operations are then completed and computation and v=1 (and a u g the Precinct is P as Verified is initiated by pressing the button of the start switch. 45 by ta 1 in W33 and signal H agreeing in value with The computer then enters its normal Preexchange block each the P g pp Will hi5 Set 10 its 1 program, designated as entry 4 i Tabl 2, state, so that the computer thereupon enters into its Write (4) The computer is in its Preexchange block program Pr g am =1, 3 :0, t *=0).

(13 :0, 13 :0, *=1), cnmputation i performed If precinct is not verified in W33, Postexchange will upon the words of the L block (B11). When computahold pp l Will not be and Signal Will be tion is com leted, aux instruction a earin in W33 a d erased. (returneq m 0 value) upon the appearance of p pp g n tab 1,, 111 a word in which tab t does not appear. Normal assumed to be only in W33) of the L o k is accepted Postexchange operation then continues until tab coinciand Immediately thereafter the appearance of the deuce (this time in the correct precinct) is again obtained,

fiducial mark the computer enters its Exchange block and u pon precinct verification lll W33, the Write roprogram 1 9 132:1, a y setting fl pp 2 gram 3 :1, 3 :0, z,*=0) is entered. P and Changing slgnfli f a 1 W a 0 (7) The computer is in its Write program (B =l,

The computer 18 m as nolrnal E g block p 13 :0, r,,*=0) which lasts for one turn of the L4; gram (B1=0: 32:1, i= Whlch W111 last for thrh channel, the B block (Btl) being written into its proper of the LB channel. Durlng this turn the L and B i i i h w h l during thi tur blocks (B11 and B12) are interchanged so that B12 be- During th W it program, as indicated by the arrow, comes the new L bl k a d B11 becomes fi new B tab t is copied into the tab t cell in each word of the hl ck. In a h w r therefore, the o and w tabs are L-B channel to thereby serve (in W3) to identify the interchanged lndlcated y the arrows) and the 1 and address of the next block (B13) to be read from the W t tabs are interchanged. Note that as a result of this h l,

Operation the new o tab P p y designates the At the completion of the turn of the L B channel (u pon blOCk address to WhlCll the Old L blOCk (B11), 110W the the next appearance of {he fidugial mark the B2 flip. new B block, 1s to be returned. flop is set to its 1 state so that the computer then enters When the turn of the L-B channel is completed (upon th fi t b 1; =1 B :1 1 *=0 f t the next appearance of the fiducial mark flip-flop B program. p 1 2 a o 1 s Read is zeroed so that the Postexchange block program It should however be noted that if tab coincidence (B =0, B =0, t *=0) isthereupon entered into. had occurred during Write, the v signal would be zeroed h p r i in i Postexchange blok P (to memorize the tab coincidence) and at the end of grarn which may last for many turns of the L-B channel. the turn of the L-B channel (assuming precinct verifica- During this program, the t tab (in W1) is used to idention were obtained) not only would the B flip-flop be 27 set but also the t,," tab would be changed to a 1 valued signal, so that the computer would enter the second phase (B =l, 8 :1, t,,*=1) of its read program. It will appear shortly that this alternative operation allows any B1, to be read from the W channel immediately after the preceding block B1 is written into the W channel.

(8) The computer is initially in the first phase (8 :1, B =1, 13*:0) of its read program. During this phase, the W channel blocks as they appear are continually copied into the B block during successive turns of the LB channel, until t -t tab coincidence occurring during a turn indicates that the desired block (B13) will appear and be copied during the next turn of the L-B channel. The v signal is zeroed to memorize such tab coincidence until the completion of the turn in which coincidence occurs.

At the completion of the turn in which tab coincidence occurs (as indicated by v= and appearance of the fiducial mark the 1; tab in W33 is changed to its 1 value (provided precinct verification is obtained) so that the computer then enters the second phase (8 :1, B =1, t *=l) of its Read program during the next turn of the L-B channel. The fact that t *=l indicates that the desired block (B13) is being read and copied during the next turn and, therefore, at the completion of this turn the Read program is ended, the flip-flops B and 13 both being zeroed so that the computer re-enters its Preexchange block program.

Note that when the desired block (B13) is copied into the B block, it carries the address of its successor block (B14) as the position (in W4) of the r tab, this tab being also copied (as shown by the arrow).

If precinct verification has not been obtained, the first phase of the Read pro-gram would continue (t,,* would not be changed to its 1 value) and the v signal would be reset to its 1 value upon the appearance of tab t in a word in which tab t does not appear. The normal first phase of the Read program would thereafter continue until tab coincidence (this time in the correct precinct) is again obtained, and upon precinct verification in W33, the second phase of the read program would be entered upon, this lasting for one turn of the L-B channel and followed by the Preexchange program.

(9)423) During the programs described by entries (9) through (23), three more complete cycles of the block programs are accomplished. Note that the described manipulations of the tabs are repeated without change in each cycle of the block programs. Note further that in the course of these manipulations each entering t tab is utilized as a 1 tab at the proper times to first control reading of the successor block from the W channel during the next block program cycle, and then to control the return of the successor block to its proper position in the W channel two program cycles later.

For example, referring to entry (8) when B13 is read into the B block, its t tab in W4 indicates that B14 is to be the successor block. As shown by entries (10) and (12), respectively, in the next block program cycle, the entering t tab appears next as a t; tab in W4 and then as t and t tabs in W4, serving at this time to control the reading of B14 from the W channel. During the Exchange program of the next cycle, entry (15), the t and r, tabs are changed to the t and t tab cells of W4. Therefore, when B13 is written back into the W channel, it carries its correct I tab in W4 to identify its successor block (B14) if B13 is ever used again. Moreover, during the Exchange program of the next cycle, entry the t tab again appears as the t tab in W4, and is utilized in entry (21) to control the writing of B14 back into the W channel. It is thus seen that the simple repetition of the described tab movements is able to accomplish quite complex block addressing operations.

It will be understood that the tab manipulations shown by Table 2, are also performed on the corresponding 28 tabs 11 t.,,*, 1 and t appearing in W33 of the L-B channel. In this manner the tabs in W33 are moved about within the word so that they are able to serve at the proper times as t tabs to thereby identify the precincts of W channel positions from which blocks are to be read or into which blocks are to be written.

DEVIATIONS FROM NORMAL BLOCK PROGRAM CYCLE As shown in Table 2, the block programs appear in their normal sequence. However as was hereinbefore mentioned a number of deviations from this sequence are possible. These are listed for purposes of convenience.

(1) If the 3( (Exchange) instruction appears and is accepted in W32 as well as in W33, Exchange is followed by Preexchange. This allows a pair of L and B blocks to be computed upon as long as desired until (as a result of a test instruction) the 3( instruction in W32 is not ac- VALUES OF THE v SIGNAL As explained in connection with Table 2, the v signal in the X channel is utilized to store or memorize the occurrence of tab coincidence during the course of the block addressing operations. The described operations upon the v signal are briefly summarized in the following table, Table 3:

From 'a consideration of Table 3, it becomes clear that a tab coincidence noted during Exchange or Preexchange or Postexchange (by setting v=l) automatically loses that significance once Write or Read is entered since during Write the normal value of v is 1 and tab coincidence is memorized by zeroing v.

Similarly a tab coincidence noted during Write or Read (by zeroing v) automatically loses that significance, once Preexchange is entered.

DETAILED DESCRIPTION OF STRUCTURE AND OPERATION Virtually all of the operations of the computer have now been described with varying particularity in the general description of operation provided in the preceding portions of this specification. All of the above described operations of the computer will now be reviewed in detail both to further clarify the nature of the operations performed and to fully disclose the electrical circuits and apparatus utilized in a preferred embodiment of the computer to mechanize these operations.

As stated before, in the operation of the computer, as indicated in Fig. 1, virtually all operations are carried on by successive changes in the states of the computer flip-flops. During each timing interval, gating matrix 20 receives bilevel signals and in response thereto at the end of the timing interval (as demarked by the appearance of a clock pulse Cl) selectively produces set and zero signals which are applied to the corresponding inputs of the computer flip-flops to set, zero or trigger" the flip-flops. Matrix 20 also produces the pair of gate control signals B B; and B' +B and also the output signals Start Tape, Stop Tape, Warning and Number.

It will be shown that gating matrix 20 comprises a plurality of gating networks, each gating network receiv ing some of the signals applied to the gating matrix and combining these signals to form one of the output signals produced by the gating matrix. Thus gating matrix 20 includes one gating network for producing the SI input signal, a second gating network for producing the 21 signal and so forth, there being one gating network respectively for each of the output signals produced by gating matrix 20. Each of the gating networks will ordinarily include a plurality of logical and gates and or gates arranged to combine applied signals in accordance with an associated Boolean logical equation to produce a desired resultant output signal. As is well known in the art, the Boolean equation associated with a gating network fully defines the output signal produced by the network in terms of the input signals received by the network and in addition supplies a complete description of the structure of the gating network.

For example, referring now to Fig. 4, there are illustrated two gating networks 101 and 102, respectively, which form the output signal SI and 21 respectively, these signals, as illustrated in Figs. 1 and 4, being applied to flip-flop I to respectively set and zero the flip-flop. In reference to their functions, gating network 101 will be referred to as Set I Gating Network 101 and gating network 102 as Zero I Gating Network 102. Other gating networks will be similarly designated in terms of the output signals they produce.

As will be shown Set I and Zero I Gating Networks 101 and 102 as shown in Fig. 4 are respectively mechanized in strict accordance with the terms of corresponding Boolean logical Equations 1 and 2, provided hereinbelow.

In Eqs. 1 and 2 the presence of a indicates that the logical or operation is to be performed on the expressions joined thereby while the absence of a indicates that the logical an operation is to be performed on the expressions joined thereby. A bracket I parentheses, or similar expression also indicates that the logical and operation is to be performed upon the factor outside the bracket and the expression contained within the bracket.

Thus Eq. 2 states in a very concise form that an out put pulse 21 will be produced only when signals I and T and X' and X are at their high (1 representing) levels a clock pulse Cl appears. Eq. 2 also provides an exact and literal description of the corresponding structure of Zero I Gating Network 102. As shown in Fig. 4, gating network 102 comprises two conventional diode and" gates 83 and 84. And gate 83 mechanizes the expression lTX X in Eq. 2 and is therefore a four input terminal gate to whose terminals the bilevel signals I, T, X' X, are respectively applied, gate 83 combining these applied signais in accordance with the logical and operation to produce a bilevel output signal designated as signal ITX X which has a high level only when all of the signals I and T and X and X are at their high levels.

As shown in Fig. 4, to complete the mechanization of Eq. 2 the signal ITX X is applied to one input terminal of the two input and" gate 84 symbolically represented in Fig. 4 as a semi-circle with a dot in the center, the clock pulses Cl being applied to a second input terminal of gate 84. Gate 84 is effective to produce an output pulse signal CIHTXHX only when signal ITX X is at a high level and a clock pulse Cl appears. This output pulse signal as shown in Fig. 4 is output signal 21 as defined by Eq. 2.

As another example, consider the mechanization of Boolean Eq. 1 by corresponding gating network 101 to produce the SI input signal. Eq. 1 indicates that the SI input signal is to be produced only when signals 1' and T and X and X, are all high, or when signals M and O and 0 and I and T and X 3121 X are all high, and in addition a clock pulse CI is applied. In mechanizing the expression IT'X X a four input an gate 85 is utilized which receives signals I, T, X, and

X and combines them to produce a corresponding output signal IT'X X The expression M O O ITX X is mechanized by a seven input and" gate 86 which combines the corresponding signals M 0 0 I, T, X

and X The signals produced by gates 85 and 86 are applied to a conventional or gate 87 which combines these signals to produce an output signal designated as [lTX x -t-M O O lTX X which is at a high level whenever any of the two applied signals I'T'X X o r M O O IT'X X is at its high level. The signal produced by gate 87 is applied to one terminal of an and" gate 88 which receives clock pulses Cl at its other terminal, gate 87 functioning to produce a pulse output signal whenever the signal [I'T'X X -i-ll O O I'T'X X is at its high level and a clock pulse Cl appears. This pulse output signal is the required SI signal as defined by Eq. 1.

It is apparent from the preceding discussion that logical Eqs. 1 and 2 completely specify the structure of the corresponding gating networks 101 and 102, that is, each equation specifies the number of and and or" gates which are to be included in the gating network, the number of inputs to each corresponding gate and the interconnection between the gates. Similar discussions of the manner in which Boolean logical equations may be mechanized by corresponding gating networks have appeared in a variety of prior art publications, as for example in an article entitled An Algebraic Theory for Use in Digital Computer Design, by E. C. Nelson, found in the Transactions of the IRE Professional Group on Electronic Computers, September 1954 issue, pages 12 through 21. Accordingly, for the purpose of facilitating complete understanding of the structure and operation of the present invention, the remainder of this specification will be largely devoted to a derivation of the logical equations which describe the operation and specify the structure 

